This invention relates to a voltage level converting circuit and, more particularly, to a voltage level converting circuit as an input interface to a logic device.
To operate a TTL (transistor transistor logic) device in response to the output signal of an ECL (emitter coupled logic) device, a voltage level converting circuit is provided at the prestage of the TTL device. The reason for this is that the amplitude of the output signal of the ECL device is relatively small and varies in a voltage range which is unacceptable for the input signal variation range of the TTL device.
FIG. 1 shows a voltage level converting circuit of prior art. As shown, this circuit has npn transistors 11 and 12 as a differential pair. The bases of the transistors 11 and 12 are connected to input terminals 13A and 13B, respectively. The input terminal 13A receives the output signal of an ECL circuit, for example, while the input terminal 13B receives the inverted one. The collector of the transistor 12 is connected to a first potential terminal 17 through series connected resistors 14 to 16. The emitter of the transistor 12 is connected to the emitter of the transistor 11 and, through a resistor 18, to a second potential terminal 19. The collector of the transistor 11 is connected to the emiter of an npn transistor 20. The collector of the transistor 11 is connected to the first potential terminal 17. The base of the transistor 20 is connected to the base of an npn transistor 21. The base of the transistor 21 is connected to its collector which, in turn, is connected to the first potential terminal 17 by way of a resistor 22. The emitter of the transistor 21 is connected to the collector of the transistor 12 and a ground potential terminal 23. The emitter of the transistor 20 is connected to the junction between the resistors 14 and 15 and the base of an npn transistor 24. The collector of the transistor 24 is connected to an output terminal 25, and the emitter thereof to the ground potential terminal 23. The base and the collector of the npn transistor 24 are coupled with the junction between the resistors 15 and 16. The emitter of the transistor 24 is connected to the output terminal 25. A resistor 26, formed, for example, in a TTL device, is connected between the first potential terminal 17 and the output terminal 25.
In the voltage level converting circuit thus aranged, a potential difference between the input terminals 13A and 13B selectively renders either of the transistors 11 and 12 conductive. When, for example, the output signal of the ECL device is of a high voltage level, the transistors 11 and 12 are turned on and off, respectively. Then, the junction between the resistors 14 and 15 is set at 0 V (i.e., ground level), thereby off the transistor 24. The potential of 0 V is determined in the following manner. Assuming that the voltage drop across the base-emitter path of each of the transistors 20 and 21 is V.sub.BE, the base potential of transistor 20 is always higher by V.sub.BE than the emitter potential of the transistor 21. When the transistor 11 is conductive, the emitter current of the transistor 20 flows into the transistor 11, not the resistor 14; the emitter potential of the transistor 20 is set to be V.sub.BE lower than its base potential. Thus, the emitter potential of the transistor 20 is set at the ground level, equal to the emitter potential of the transistor 21.
When the output signal of the ECL device is of a low voltage level, the transistors 12 and 11 are turned on and off, respectively. The current from the resistor 15 and the emitter current from the transistor 20 is supplied to the resistor 14. The transistor 24 is turned on by the voltage drop across the resistor 14.
The voltage level converting circuit described above can convert the voltage signal within the ECL range into that within the TTL range. This circuit, however, requires two power sources corresponding to the first and second potential terminals 17 and 19, as well as many further circuit elements, particularly bipolar transistors.
FIG. 2 shows a response characteristic of this voltage level converting circuit. This characteristic was ploted as the result of the SPICE simulation. In this simulation, the collector currents of the transistors 11 and 12 in the conductive state was set at 500 .mu.A, and the collector current of the transistor 24 in the conductive state was 400 .mu.A. As seen from FIG. 2, the output signal of the voltage level converting circuit takes a relatively long time to reach a predetermined level. In order that this converting circuit responds to a logic signal of about 10 MHz at a satisfactorily high speed, the collector current of the transistor 24 must be set to at least 1 mA. Under these circumstances, however, the conveting circuit dissipates much power.
FIG. 3 shows another voltage level converting circuit of prior art. As shown, this voltage level converting circuit comprises, at its input stage, a differential pair of pnp transistors 30 and 31, as well as, at the output stage, both an npn transistor 32 and a pnp transistor 33. A first potential terminal 28 is connected to the emitters of the transistors 30 and 31 by way of a resistor 35 . A second potential terminal 29 is connected through a resistor 36 to the collector of the transistor 30, and directly connected to the collector of the transistor 31. The collector of the transistor 30 is connected to the base of the transistor 32. The conduction state of the transistor 32 is under control of the voltage drop across the resistor 36. The transistor 32 is connected at the emitter to the second potential terminal 29, and at the collector to the output terminal 39. The first potential terminal 28 is connected to the collector of the transistor 32 through a resistor 38 and the current path of a transistor 33. The transistor 33, supplied at the base with a bias voltage VB, prevents the transistor 32 from operating in the saturation region.
In operation, when a high level voltage is applied as an input signal to the first input signal 34A, and a low level voltage is applied as an inverted input signal to the second input terminal 34B, the transistor 30 is turned off and the transistor 31 is turned on. Under this condition, the base of the transistor 32 is at substantially the same potential as that the terminal 29, so that the transistor 32 is turned off. At this time, the potential at the output terminal 39 is substantially equal to the high level potential at the first terminal 28. When a low level voltage is applied as an input signal to the first input terminal 34A, and a high level voltage is applied as an inverted input signal to the second input terminal 34B, the transistor 30 is turned on and the transistor 31 is turned off. Under this condition, current flows from the terminal 28 into the resistor 36 through the resistor 35 and the emitter-collector path of the transistor 30. This current causes a voltage drop across the resistor 36. The voltage drop biases the transistor 32 appropriately, turning it on. When the transistor 32 is turned on, the terminal 39 is grounded through the transistor 32. Accordingly, the potential at the terminal 39 is substantially equal to the ground potential, i.e., the potential at the terminal 29.
This voltage level converting circuit employs a single power source for converting the input voltage within the ECL range into the output voltage within the TTL range. In this converting circuit the pnp transistor 33 is connected, in cascade fashion, to the npn transistor 32 in order to prevent the transistor 32 from operating in the saturation region. Such a connection is unpreferable because the pnp transistor is not capable of high speed performance. Therefore, the operating speed of this prior converting circuit is slow. Additionally, this converting circuit, as in the prior converting circuit of FIG. 1, consumes much power.